Analog IC
The W5500 chip is an embedded Ethernet controller with integrated hardware TCP/IP protocol stack, which provides a simpler, faster, more stable and more secure Ethernet access solution for microcontrollers.
The all-hardware TCP/IP protocol stack is a patented product of WIZnet, which aims to simplify the traditional software TCP/IP protocol stack, offload the threads used by the MCU to process TCP/IP, save hardware resources such as internal ROM of the MCU, and engineers only need to carry out simple socket programming and a small number of register operations to easily develop embedded Ethernet upper-layer applications, reduce product development cycles, and reduce development costs.
The W5500 supports a high-speed standard 4-wire SPI interface to communicate with the host, which can theoretically reach 80MHz. It also integrates the Ethernet Data Link Layer (MAC) and 10BaseT/100BaseTX Ethernet Physical Layer (PHY) with support for auto-negotiation (10/100-based full-duplex/half-duplex), power-down mode, and Wake-on-LAN functionality. Different from the traditional software protocol stack, the W5500 can have 8 independent hardware sockets for 8 independent communication channels, and the communication efficiency of the 8 sockets does not affect each other, and the size of each socket can be flexibly defined through the 32K bytes of receive/receive cache on the W5500 chip.
W5500 is also an industrial-grade Ethernet control chip, which is rapidly occupying the market with its high performance, good performance and high cost performance, and has been unanimously recognized by industry users.
Fields of application
Smart grids
Financial equipment
Security access control
Gateway devices
Smart home
Smart home
Peculiarity
Full hardware TCP/IP protocol stack
– Support TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE protocols
– Hardware network engine, protected from cyber attacks
High-speed SPI host interface
– SPI mode: 0,3
– SPI clock up to 80MHz
Embedded operating system support: Linux & RTOS
It supports 8 independent hardware sockets for simultaneous communication, and the communication efficiency does not affect each other
Internal 32K byte transceiver cache for TCP/IP packet processing
Support power-down mode and wake-on-net
Integrated 10BaseT / 100Base-T Ethernet PHY
Support auto-negotiation (full/half-duplex, 10M/100M)
Automatic polarity translation is not supported (one of the two sides of the network communication can support it)
Network status indicator pins, including network speed indicator (10M/100M), data sce/receive activity indicator, full/half-duplex status indicator, and PHY connection status indicator
Industrial grade: -40°C ~ 85°C
The operating voltage is 3.3V, and the I/O is 5V
48-Pin LQFP Pb-Free Package (7x7mm, 0.5mm Pin Pitch)
